Boolean Processor

ABSTRACT

A processor including a Boolean logic unit, wherein the Boolean logic unit is operable for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, a plurality of input/output interfaces, wherein the plurality of input/output interfaces are operable for receiving a plurality of compiled Boolean expressions/operations and transmitting a plurality of compiled results, and a plurality of registers. An associated processing method including starting an operation related to a Conjunctive Normal Form Boolean expression, wherein the Boolean expression comprises a conjunct, evaluating the conjunct, and selectively short-circuiting a portion of the Boolean expression.

CROSS-REFERENCE TO RELATED APPLICATIONS

This non-provisional patent application is a divisional of U.S. patentapplication Ser. No. 10/075,917, filed Feb. 13, 2002 and claims thebenefit of U.S. Provisional Patent Application Nos. 60/268,471,60/268,472, and 60/268,478, each filed Feb. 14, 2001, the entirety ofall of which are hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates generally to the computing andmicroelectronics fields. More specifically, the present inventionrelates to a Boolean-based processor architecture that is capable of theshort-circuit evaluation of Conjunctive Normal Form (CNF) Booleanexpressions. The Boolean processor of the present invention provides aninexpensive, scalable, and efficient means for computing in environmentstypically suited for application-specific microprocessors andmicrocontrollers, such as monitoring and automation environments.

BACKGROUND OF THE INVENTION

A microprocessor is a general-purpose computing architecture, also knownas a central processing unit (CPU). The microprocessor includes anarithmetic logic unit (ALU), an accumulator, a plurality of registers, aprogram counter, a stack pointer, a clock circuit, and a plurality ofinterrupt circuits. In building a complete computing system, themicroprocessor must be supplemented with external components, such as arandom-access memory (RAM) and a read-only memory (ROM), an oscillator,a plurality of memory decoders, a plurality of Input/Output (I/O)interfaces (ports), and a plurality of other devices, such as videodisplays and disk drives. The microprocessor is designed to perform awide variety of calculations with data and return the results to a useror another machine. The microprocessor achieves this computing powerthrough the use of a sophisticated instruction set that may contain aplurality of instructions for performing arithmetic operations, bitmovement operations, memory fetch and store operations, etc. Because ofthe complexity of the calculations that the microprocessor performs, theprograms that control its operation are generally relatively large,requiring the use of mass storage devices to house them. When needed fora specific calculation or task, a program is loaded into the system RAMand executed by the microprocessor.

The primary design factors related to the microprocessor are flexibilityand expandability, allowing the microprocessor to handle almost anytask. This adaptability has resulted in a relatively large demand forthe microprocessor and has enabled manufacturers to mass-produce them,resulting in a relatively inexpensive and disposable product.

Like the microprocessor, a microcontroller is also a general-purposecomputing architecture. The microcontroller differs from themicroprocessor, however, in that it can operate as a complete,stand-alone computer system. The microcontroller includes all of thecomponents of the microprocessor, in addition to its own RAM, ROM,plurality of counters, and I/O ports. The microcontroller is alsorelatively flexible and can be used in a plurality of applications,however, the microcontroller is intended for use in a relatively staticenvironment, requiring its programs to change minimally over time. Themicrocontroller is primarily intended to be used to control theenvironment within which it operates. The microcontroller is typicallyused in embedded system applications for monitoring and automationpurposes. The microcontroller can be found in, for example, appliances(such as microwave ovens, refrigerators, televisions, VCRs, andstereos), automobiles (such as in engine control systems, diagnosticssystems, and climate control systems), environmental control systems(such as in factories, greenhouses, and homes), instrumentation arrays,and aerospace systems.

The microprocessor differs from the microcontroller in their sets ofoperational codes. The microprocessor has far more operational codes formoving data to and from an external memory than the microcontroller,which may only have a few such operational codes. From an internalbit-handling perspective, the microcontroller has far more internalbit-handling operational codes than the microprocessor, which may onlyhave a few. The architecture of both the microprocessor and themicrocontroller are intended for mass use and are designed forflexibility and expandability. Each has the goal of supporting a widerange of applications. While the primary use of the microprocessor isfor calculation-intensive computing, the microcontroller is designed tohandle smaller calculations and to control its environment.

The short-circuit evaluation of a Boolean expression or operation issimply the abandonment of the remainder of the expression or operationonce its value has been determined. If the outcome of the expression oroperation can be determined prior to its full evaluation, it makes senseto save processing cycles by avoiding the remaining, unnecessary,conditional tests of the expression or operation. In other words, theshort-circuit evaluation of a Boolean expression is a technique thatspecifies the partial evaluation of the expression involving an AND andan OR operation.

What is needed is a microprocessor and/or a microcontroller that iscapable of evaluating complex Boolean expressions that are inConjunctive Normal Form (CNF). Disjunctive Normal Form (DNF) Booleanexpressions can also be incorporated into the architecture of themicroprocessor and/or the microcontroller, however, there areinefficiencies associated with the processing of the DNF equivalents ofCNF expressions.

A Boolean expression is in DNF if it is expressed as the sum (OR) ofproducts (AND). That is, the Boolean expression B is in DNF if it iswritten as:

A1 OR A2 OR A3 OR . . . An,

where each term Ai is expressed as:

T1 AND T2 AND . . . AND Tm,

where each term Ti is either a simple variable, or the negation (NOT) ofa simple variable. Each term Ai is referred to as a “minterm”. A Booleanexpression is in CNF if it is expressed as the product (AND) of sums(OR). That is, the Boolean expression B is in CNF if it is written as:

O1 AND O2 AND O3 AND . . . On,

where each term Oi is expressed as:

T1 OR T2 OR . . . OR Tm,

where each term Ti is either a simple variable, or the negation (NOT) ofa simple variable. Each term Oi is referred to as a “maxterm”. The terms“minterm” and “maxterm” can also be referred to as “disjunct” and“conjunct”, respectively.

The short-circuit evaluations of a CNF Boolean expression and a DNFBoolean expression are handled differently. In the case of a CNFexpression, short-circuiting can occur if any of the conjuncts evaluatesto false. In the following example,

(A

B)

(C

D),

if either of the conjuncts, (A

B) or (C

D), evaluates to false, the expression also evaluates to false. If (A

B) evaluates to false, the remainder of the expression can beeliminated, thereby saving the time required to evaluate the otherconjunct. In contrast to CNF short-circuit evaluation, a DNF expressioncan be short-circuited if any of the disjuncts evaluates to true. Usingthe previous example in DNF,

(A

C)

(A

D)

(B

C)

(B

D),

if any of the disjuncts, (A

C), (A

D), (B

C), or (B

D), evaluates to true, the expression also evaluates to true. Forexample, if (A

C) evaluates to true, the evaluation of the remaining three disjunctscan be eliminated, since their values are irrelevant to the outcome ofthe expression.

Thus, the short-circuit evaluation of both CNF and DNF expressionsbecomes increasingly valuable, in terms of cycle savings, as thecomplexity of the expressions increases. In large scale monitoring andautomation applications, the short-circuit evaluation of both CNF andDNF expressions is essential.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the general-purpose Boolean processor of the presentinvention incorporate an architecture that is designed to provideoptimal performance for computing complex Boolean expressions. TheBoolean processor is intended for use in, among other things, monitoringand automation applications. The Boolean processor is built for speedand efficiency via its ability to perform the short-circuit evaluationof Conjunctive Normal Form (CNF) Boolean expressions. The Booleanprocessor provides enhanced computing performance, in terms of thenumber of instructions required to perform equivalent operations, tothat of other general-purpose architectures.

In one embodiment of the present invention, a processor includes aBoolean logic unit, wherein the Boolean logic unit is operable forperforming the short-circuit evaluation of Conjunctive Normal FormBoolean expressions/operations, a plurality of input/output interfaces,wherein the plurality of input/output interfaces are operable forreceiving a plurality of compiled Boolean expressions/operations andtransmitting a plurality of compiled results, and a plurality ofregisters.

In another embodiment of the present invention, a processing methodincludes starting an operation related to a Conjunctive Normal FormBoolean expression, wherein the Boolean expression comprises a conjunct,evaluating the conjunct, and selectively short-circuiting a portion ofthe Boolean expression.

In a further embodiment of the present invention, a device polling unitfor finding new devices, assigning addresses to those devices, pollingthose devices for their current states, and updating a random-accessmemory with those states includes a maximum device addresselectrically-erasable programmable read-only memory, wherein theelectrically-erasable programmable read-only memory is operable forstoring the highest address of all known devices on a system, whereinthe electrically-erasable programmable read-only memory includes anincrement line that increments its value by one whenever it is assertedand a plurality of output lines that continuously output its value. Thedevice polling unit also includes an n-bit incrementing register,wherein the n-bit incrementing register is operable for holding an n-bitnumber representing a current address of a device being polled, whereinthe n-bit incrementing register includes a reset line that sets theregister to ‘zero’ whenever it is asserted, and wherein the n-bitincrementing register further includes an increment line and a pluralityof output lines that continuously output its value to an AND unit and acurrent address encoder. The device polling unit operates in acontinuous loop after it is started.

In a further embodiment of the present invention, a device interfaceunit for listening for new device seek, new address, state enable, andcontrol line assertions and determining whether or not there is work todo as a result of such assertions includes a new deviceelectrically-erasable programmable read-only memory, wherein the newdevice electrically-erasable programmable read-only memory includes ann-bit store that is initially set to ‘one’, and wherein, when a newdevice seek line is asserted, the n-bit store asserts a new device foundline. The device interface unit also includes an address decoder,wherein, if the n-bit store is set, it allows an address passed on a newaddress line to be placed in an n-bit address electrically-erasableprogrammable read-only memory and the n-bit store to be cleared. Thedevice interface unit further includes a control word decoder, whereinthe control word decoder is operable for reading serial bits off of acontrol line, and wherein, if an address matches the address in then-bit address electrically-erasable programmable read-only memory, aplurality of control bits output to a device controller to change itsstate. The device interface unit further includes an address and stateencoder, wherein the address and state encoder is operable for readingbits in parallel that represent the address and state of the device andserially outputs the bits to a receiver.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of a conventional microprocessor;

FIG. 2 is a schematic block diagram of a conventional microcontroller;

FIG. 3 is a schematic block diagram of one embodiment of the Booleanprocessor of the present invention;

FIG. 4 is a schematic diagram of one embodiment of the architecture ofthe Boolean processor of the present invention;

FIG. 5 is a graph of a DNF/CNF ratio using inter-term short-circuitevaluation, with 1 control state and a small number of “other” states;

FIG. 6 is a graph of a DNF/CNF ratio using inter-term short-circuitevaluation, with 1 control state and a large number of “other” states;

FIG. 7 is a graph of a DNF/CNF ratio using inter-term short-circuitevaluation, with 5 control states and a small number of “other” states;

FIG. 8 is a graph of a DNF/CNF ratio using inter-term short-circuitevaluation, with 5 control states and a large number of “other” states;

FIG. 9 is a graph of a DNF/CNF ratio using inter-term short-circuitevaluation, with 10 control states and a small number of “other” states;

FIG. 10 is a graph of a DNF/CNF ratio using inter-term short-circuitevaluation, with 10 control states and a large number of “other” states;

FIG. 11 is a graph of a DNF/CNF ratio using inter/intra-termshort-circuit evaluation, with 1 control state and a small number of“other” states;

FIG. 12 is a graph of a DNF/CNF ratio using inter/intra-termshort-circuit evaluation, with 1 control state and a large number of“other” states;

FIG. 13 is a graph of a DNF/CNF ratio using inter/intra-termshort-circuit evaluation, with 10 control states and a small number of“other” states;

FIG. 14 is a graph of a DNF/CNF ratio using inter/intra-termshort-circuit evaluation, with 10 control states and a large number of“other” states;

FIG. 15 is a graph of the relative performance of the Intel 8051microcontroller versus the Boolean processor of the present invention;

FIG. 16 is a graph of the relative performance of the Intel 8086 familyof microprocessors versus the Boolean processor of the presentinvention;

FIG. 17 is a graph of the relative performance of the Motorola MMC2107microcontroller versus the Boolean processor of the present invention;

FIG. 18 is a schematic diagram of one embodiment of the architecture ofthe device polling unit of the present invention;

FIG. 19 is a schematic diagram of one embodiment of the architecture ofthe device interface unit of the present invention;

FIG. 20 is a schematic diagram of one embodiment of a system thatincludes the Boolean processor and the device polling unit of thepresent invention; and

FIG. 21 is a schematic diagram of one embodiment of a system thatincludes the device interface unit of the present invention and ndevices.

DETAILED DESCRIPTION OF THE INVENTION

A microprocessor is a general-purpose computing architecture, also knownas a central processing unit (CPU). Referring to FIG. 1, themicroprocessor 10 includes an arithmetic logic unit (ALU) 12, anaccumulator 14, a plurality of registers 16, a program counter 18, astack pointer 20, a clock circuit 22, and a plurality of interruptcircuits 24. In building a complete computing system, the microprocessor10 must be supplemented with external components, such as arandom-access memory (RAM) and a read-only memory (ROM), an oscillator,a plurality of memory decoders, a plurality of Input/Output (I/O)interfaces (ports), and a plurality of other devices, such as videodisplays and disk drives. The microprocessor 10 is designed to perform awide variety of calculations with data and return the results to a useror another machine. The microprocessor 10 achieves this computing powerthrough the use of a sophisticated instruction set that may contain aplurality of instructions for performing arithmetic operations, bitmovement operations, memory fetch and store operations, etc. Because ofthe complexity of the calculations that the microprocessor 10 performs,the programs that control its operation are generally relatively large,requiring the use of mass storage devices to house them. When needed fora specific calculation or task, a program is loaded into the system RAMand executed by the microprocessor 10.

The primary design factors related to the microprocessor 10 areflexibility and expandability, allowing the microprocessor 10 to handlealmost any task. This adaptability has resulted in a relatively largedemand for the microprocessor 10 and has enabled manufacturers tomass-produce them, resulting in a relatively inexpensive and disposableproduct.

Like the microprocessor 10, a microcontroller is also a general-purposecomputing architecture. The microcontroller differs from themicroprocessor 10, however, in that it can operate as a complete,stand-alone computer system. Referring to FIG. 2, the microcontroller 26includes all of the components of the microprocessor 10 (FIG. 1), inaddition to its own RAM 28, ROM 30, plurality of counters 32, and I/Oports 34. The microcontroller 26 is also relatively flexible and can beused in a plurality of applications, however, the microcontroller 26 isintended for use in a relatively static environment, requiring itsprograms to change minimally over time. The microcontroller 26 isprimarily intended to be used to control the environment within which itoperates. The microcontroller 26 is typically used in embedded systemapplications for monitoring and automation purposes. The microcontroller26 can be found in, for example, appliances (such as microwave ovens,refrigerators, televisions, VCRs, and stereos), automobiles (such as inengine control systems, diagnostics systems, and climate controlsystems), environmental control systems (such as in factories,greenhouses, and homes), instrumentation arrays, and aerospace systems.

The microprocessor 10 differs from the microcontroller 26 in their setsof operational codes. The microprocessor 10 has far more operationalcodes for moving data to and from an external memory than themicrocontroller 26, which may only have a few such operational codes.From an internal bit-handling perspective, the microcontroller 26 hasfar more internal bit-handling operational codes than the microprocessor10, which may only have a few. The architecture of both themicroprocessor 10 and the microcontroller 26 are intended for mass useand are designed for flexibility and expandability. Each has the goal ofsupporting a wide range of applications. While the primary use of themicroprocessor 10 is for calculation-intensive computing, themicrocontroller 26 is designed to handle smaller calculations and tocontrol its environment.

The short-circuit evaluation of a Boolean expression or operation issimply the abandonment of the remainder of the expression or operationonce its value has been determined. If the outcome of the expression oroperation can be determined prior to its full evaluation, it makes senseto save processing cycles by avoiding the remaining, unnecessary,conditional tests of the expression or operation. In other words, theshort-circuit evaluation of a Boolean expression is a technique thatspecifies the partial evaluation of the expression involving an ANDand/or an OR operation, or a plurality of each.

What is needed is a microprocessor and/or a microcontroller that iscapable of evaluating complex Boolean expressions that are inConjunctive Normal Form (CNF). Disjunctive Normal Form (DNF) Booleanexpressions can also be incorporated into the architecture of themicroprocessor and/or the microcontroller, however, there areinefficiencies associated with the processing of the DNF equivalents ofCNF expressions.

A Boolean expression is in DNF if it is expressed as the sum (OR) ofproducts (AND). That is, the Boolean expression B is in DNF if it iswritten as:

A1 OR A2 OR A3 OR . . . An,  (1)

where each term Ai is expressed as:

T1 AND T2 AND . . . AND Tm,  (2)

where each term Ti is either a simple variable, or the negation (NOT) ofa simple variable. Each term Ai is referred to as a “minterm”. A Booleanexpression is in CNF if it is expressed as the product (AND) of sums(OR). That is, the Boolean expression B is in CNF if it is written as:

O1 AND O2 AND O3 AND . . . On,  (3)

where each term Oi is expressed as:

T1 OR T2 OR . . . OR Tm,  (4)

where each term Ti is either a simple variable, or the negation (NOT) ofa simple variable. Each term Oi is referred to as a “maxterm”. The terms“minterm” and “maxterm” can also be referred to as “disjunct” and“conjunct”, respectively.

The short-circuit evaluations of a CNF Boolean expression and a DNFBoolean expression are handled differently. In the case of a CNFexpression, short-circuiting can occur if any of the conjuncts evaluatesto false. In the following example,

(A

B)

(C

D),  (5)

if either of the conjuncts, (A

B) or (C

D), evaluates to false, the expression also evaluates to false. If (A

B) evaluates to false, the remainder of the expression can beeliminated, thereby saving the time required to evaluate the otherconjunct. In contrast to CNF short-circuit evaluation, a DNF expressioncan be short-circuited if any of the disjuncts evaluates to true. Usingthe previous example in DNF,

(A

C)

(A

D)

(B

C)

(B

D),  (6)

if any of the disjuncts, (A

C), (A

D), (B

C), or (B

D), evaluates to true, the expression also evaluates to true. Forexample, if (A

C) evaluates to true, the evaluation of the remaining three disjunctscan be eliminated, since their values are irrelevant to the outcome ofthe expression.

Thus, the short-circuit evaluation of both CNF and DNF expressionsbecomes increasingly valuable, in terms of cycle savings, as thecomplexity of the expressions increases. In large scale monitoring andautomation applications, the short-circuit evaluation of both CNF andDNF expressions is essential.

Referring to FIG. 3, in one embodiment of the present invention, thearchitecture of the Boolean processor 36 can best be described as thatof a microcontroller, at least functionally. The inputs of themicrocontroller are compiled Boolean operations, or tests, and theoutputs of the microcontroller are compiled result operations that areexecuted in conjunction with the results of the tests. The Booleanprocessor 36 includes a clock circuit 22, a program counter 18, aplurality of Input/Output (I/O) interfaces (ports) 34, a plurality ofregisters 16, a random-access memory (RAM) 28, and a read-only memory(ROM) 30. The Boolean processor 36 differs, however, from a conventionalmicrocontroller in that the Boolean processor 36 does not contain anaccumulator 14 (FIGS. 1 and 2), a plurality of counters (other than theprogram counter 18), a plurality of interrupt circuits 24 (FIGS. 1 and2), or a stack pointer 20 (FIGS. 1 and 2). Additionally, in lieu of anarithmetic logic unit (ALU) 12 (FIGS. 1 and 2), the Boolean processor 36includes a Boolean logic unit (BLU) 38. In terms of its size, speed, andfunctionality, the architecture of the Boolean Processor 36 is designedto be inexpensive, scalable, and efficient. The Boolean processor 36achieves these benefits through a simple design that is optimized forperforming the short-circuit evaluation of complex Conjunctive NormalForm (CNF) Boolean expressions.

The architecture of the Boolean processor 36 is illustrated in FIG. 4.For the purposes of describing the architecture of the Boolean processor36, 8-bit device addressing and 8-bit control words are used. Thisresults in the architecture of the Boolean processor 36 supporting 256devices, each device having 256 possible states. Optionally, thearchitecture of the Boolean processor 36 can be scaled to accommodate2^(n) devices, each device having 2^(m) possible states, where n and mare the number of device address bits and the number of possible statesfor each device, respectively. The defining feature of the architectureof the Boolean processor 36 is its set of registers, or lack thereof. Incontrast to conventional microprocessors and microcontrollers, which canhave a plurality of registers (typically from 8 to 64 bits wide), theBoolean processor 36 has only six registers. Of the six registers, theinstruction register 40, the next operation register 42, and the end ofOR address register 44 are the only multi-bit registers. The remainingthree registers are single-bit registers, which hold AND truth states,OR truth states, and an indicator for conjuncts containing OR clauses.

The Boolean processor 36 includes the instruction register 40, which isan n+m+3-bit wide register containing an n-bit address, an m-bitcontrol/state word, and a 3-bit operational code. Using 8-bit deviceaddressing and 8-bit control words, the instruction register 40 is19-bits wide. The Boolean processor 36 also includes a control store(ROM) 46, which is used to hold a compiled micro-program, including(n+m+3)-bit instructions. The Boolean processor 36 further includes theprogram counter 18, which is used for fetching the next instruction fromthe control store 46. The Boolean processor 36 further includes a memory(MUX) 48, which is used to configure the program counter 18 for normaloperation, conditional jump operation, unconditional jump operation, andBoolean short-circuit operation. Six AND gates 50 and one OR gate 52 areused to pass operation results and a plurality of signals that areoperational code dependent. A 1-bit AND register 54 is used to roll upthe results of the conjuncts. The default value of the 1-bit ANDregister 54 is one and it initializes to a value of one after a start ofoperational code. The 1-bit AND register 54 remains at a value of one ifall of the conjuncts in the Boolean expression being evaluated are true.If this bit is set to zero at any time during the evaluation, the entireCNF operation is false. In such a case, the remainder of the operationmay be short-circuited and the evaluation of the next operation canbegin. A 1-bit OR register 56 is used to roll up the results of all ofthe individual conjuncts. It initializes to a value of zero and remainsin that state until a state in a conjunct evaluates to one. A 1-bit ORconjunct register 58 is used to indicate that the evaluation of aconjunct containing OR clauses has begun. It initializes to a value ofzero and remains in that state until an OR operation sets its value toone. In the event that the 1-bit OR conjunct register 58 is set to oneand the 1-bit OR register 56 is set to one, the entire conjunctevaluates to true and short-circuits to the start of the next conjunct.The Boolean processor 36 further includes an operation decoder 60, whichdeciphers each operational code and controls the units that aredependent upon each operational code. The functions of the operationdecoder 60 by operational code include: Boolean AND (Op Code 0), BooleanOR (Op Code 1), End of Operation (Op Code 2), No Operation (Op Code 3),Unconditional Jump (Op Code 4), Conditional Jump (Op Code 5), Start ofOperation (Op Code 6), and Start of Conjunct (Op Code 7). A controlencoder 62 accepts n+m bits in parallel (representing a device addressand control word) and outputs them across a device bus (control lines)either serially or in parallel, depending upon the architecture of thegiven device bus. The next operation address register 42 stores theaddress used for Boolean short-circuiting. Short-circuiting occurs assoon as a conjunct evaluates to false. In such a case, the address isthe address of the next operation. The end of OR address register 44stores the address of the instruction immediately following a conjunctcontaining OR clauses. It is used for the short-circuiting of conjunctsthat contain OR clauses. The Boolean processor 36 further includes adevice state storage (RAM) 64, which is responsible for storing thestates of the devices that the Boolean processor 36 monitors and/orcontrols. It has 2^(n) addresses, each of which are m-bits wide, where nis the address width and m is the control state word width, in bits.

The Boolean processor 36 evaluates micro-programs and controls itsenvironment based upon the results of the above-described evaluations.The micro-programs define the actions to be taken by devices in theevent that given Boolean tests evaluate to true. The Boolean processor36 works on the principle that the devices will be controlled based upontheir states and the states of other devices, or after some period oftime has elapsed. In order to evaluate a micro-program, conditionaltests must be compiled into CNF.

The Boolean processor 36 performs eight functions, as specified byoperational code. Op Code 0—(Boolean AND) enables the AND gate 50 thatloads the AND register 54 in the event that the conditional state of thedevice at the address in the instruction register 40 equals the statebeing tested in the instruction register 40. Op Code 1—(Boolean OR) setsthe value of the OR conjunct register 58 to one, which enablesshort-circuiting within a conjunct containing OR clauses. Op Code 2—(Endof Operation) enables the AND gate 50 that AND's the value of the ORregister 56 with the value of the AND register 54. If the AND register54 evaluates to a value of one, the control encoder 62 is enabled andthe address and control word specified in the end of operation code issent to the proper device. Op Code 3—(No Operation) does nothing. OpCode 4—(Unconditional Jump) allows the MUX 48 to receive an address froman address portion of the instruction register 40 and causes animmediate jump to the instruction at that address. Op Code5—(Conditional Jump) provides that if the AND register 54 has a value ofone, the test condition is met and the MUX 48 is enabled to receive the“jump to” address from the address portion of the instruction register40. Op Code 6—(Start of Operation) provides the address of the end ofoperation line for the current operation. This address is used toshort-circuit the expression and keep the Boolean processor 36 fromhaving to evaluate the entire CNF expression in the event that one ofthe conjuncts evaluates to zero. In addition to loading the end ofoperation address, this operation also sets the AND register 54 to oneand the OR register 56 to zero. Op Code 7—(Start of OR Conjunct)provides the address of the line immediately following the conjunct.This address is used to provide short-circuiting functionality within agiven conjunct in the event that one of the conjunct's terms evaluatesto one.

The evaluation of a CNF expression begins with Start of Operation (OpCode 6) and proceeds to the evaluation of a conjunct. A conjunct may beeither a stand-alone term (evaluated as an AND operation) or a conjunctcontaining OR clauses. In the latter case, each term of the conjunct isevaluated as part of an OR operation (Op Code 1). Each of theseoperations represents a test to determine if the state of a given deviceis equal to the state value specified in the corresponding AND or ORinstruction. If the term evaluates to true, the OR-bit is set to a valueof one. Otherwise, the OR-bit is set to a value of zero. In the case ofa stand-alone term, this value automatically rolls up to the ANDregister 54. In conjuncts containing OR clauses, the result of each ORoperation is OR'ed with the current value of the OR register 56. Thisensures that a true term anywhere in the conjunct produces a final valueof true for the entire conjunct evaluation. In the event that the ORregister 56 has a value of one and the OR conjunct register 58 is set toone, the conjunct will evaluate to true and may be short-circuited tothe next conjunct. Next, the Boolean processor 36 prepares forsubsequent conjuncts (if any additional conjuncts exist). At this point,an AND operation (Op Code 0) joins the conjuncts and the value of the ORregister 56 is rolled up to the AND register 54 by having the value ofthe OR register 56 AND'ed with the value of the AND register 54. In theevent that the OR-bit has a value of zero when the AND operation isprocessed, the AND-bit will change to a value of zero. Otherwise, theAND-bit's value will remain at one. If the AND-bit has a value of one,the next conjunct is evaluated. If the AND-bit has a value of zero, thefinal value of the CNF expression is false, regardless of the evaluationof any additional conjuncts. At this point, the remainder of theexpression may be short-circuited and the next CNF expression can beevaluated.

Preferably, the Boolean processor 36 requires that functions be compiledin CNF. A micro-code compiler builds the micro-instructions such thatthey follow a CNF logic. The logic statements for Boolean processorprograms are nothing more than IF-THEN-ELSE statements. For example: IF(Device A has State Ax), THEN (Set Device B to State By), ELSE (SetDevice C to State Cz). The logic of the IF expression must be compiledinto CNF. The expression must also be expanded into a set of expressionsAND'ed together, and AND'ed with a pre-set value of TRUE. For the CNFoperation, the pre-set value of TRUE is the initial value of the ANDregister 54 at the start of each logical IF operation. The aboveIF-THEN-ELSE statement would result in the following micro-code logic:[(Device A has State Ax)

TRUE]; if the AND statement is TRUE, then (SET Device B to State By);and if the AND statement is FALSE, then (SET Device C to State Cz).

The following are examples of how some common operations would becompiled to work with the architecture of the Boolean processor 36. Itshould be noted that the Start of Operation Instruction (Op Code 6), aswell as the Start of Conjunct Instruction (Op Code 7), have been omittedsince ROM addresses are not listed in the examples. The notation in thefollowing examples is of the form: DevX=Y, where X represents the deviceaddress and Y represents the current state of the device.

EXAMPLE 1

If (Dev1=8 or Dev2=0) and (Dev3=10 or Dev2=0) and (Dev4=1 or Dev2=0)then Dev9=20

Micro-code Sequence # Instruction Register Value Operation 1 0000000100001000 001 OR 2 00000010 00000000 001 OR 3 00000000 00000000 000 AND 400000011 00001010 001 OR 5 00000010 00000000 001 OR 6 00000000 00000000000 AND 7 00000100 00000001 001 OR 8 00000010 00000000 001 OR 9 0000000000000000 000 AND 10 00001001 00010100 010 End of Operation

EXAMPLE 2

If Dev7=22 goto 200Else goto 100

Sequence Micro-code # Instruction Register Value Operation 1 0000011100010110 001 OR 2 00000000 00000000 000 AND 3 00000000 11001000 101Conditional Jump 4 00000000 01100100 100 Unconditional Jump

A distinct characteristic of the Boolean processor 36 is the type ofexpressions it is designed to evaluate; namely expressions in CNF.Optionally, using the same single-bit register design, a DNF-basedarchitecture can also be implemented. However, the architecture of theBoolean processor 36 focuses on CNF, providing the fastest and mostscalable design.

Upon initial inspection of the two forms, CNF and DNF, an individualmight be inclined to believe that the short-circuit evaluation of DNFexpressions has benefits over short-circuited CNF expressions becausethe terms are OR'ed together and a positive result for any of the termsresults in a completed evaluation. The same argument, in the false case,can be made for CNF evaluations. If any of the terms results in a falsevalue, the entire evaluation is complete with a value of false.Additionally, CNF eliminates repeating terms, as shown in the followingexamples.

EXAMPLE 3 Conjunctive Normal Form

If Dev2=0 and (Dev1=8 or Dev3=10 or Dev4=1) then Dev9=20

Micro-code Sequence # Instruction Register Value Operation 1 0000001000000000 000 AND 2 00000001 00001000 001 OR 3 00000011 00001010 001 OR 400000100 00000001 001 OR 5 00001001 00010100 010 End of Operation

EXAMPLE 4 Disjunctive Normal Form

If (Dev2=0 and Dev1=8) or (Dev2=0 and Dev3=10) or (Dev2=0 and Dev4=1)then Dev9=20

Micro-code Sequence # Instruction Register Value Operation 1 0000001000000000 000 AND 2 00000001 00001000 000 AND 3 00000000 00000000 001 OR4 00000010 00000000 000 AND 5 00000011 00001010 000 AND 6 0000000000000000 001 OR 7 00000010 00000000 000 AND 8 00000100 00000001 000 AND9 00000000 00000000 001 OR 10 00001001 00010100 010 End of Operation

Notice, in the examples, that the testing of Dev2 is a single conjunctin the CNF expression and repeated in every disjunct in the DNFexpression. This type of term is important as the outcomes of both theCNF and DNF expressions are almost fully dependent upon their values.These terms are referred to herein as “control states” or “controldevices”. Without a positive evaluation of a control state, any Booleanexpression, whether in CNF or DNF, will evaluate to false. In the caseof CNF, the false evaluation of a control state enablesshort-circuiting, and is what provides CNF with its advantage over DNF.

In the previous examples, CNF provides a savings of five instructionsover DNF. DNF, however, has an advantage over CNF for a very smallnumber of non-control, or “other” states (one or two). As the number ofterms (both control and “other”) grows, however, the short-circuiting ofCNF expressions becomes a much more efficient means of evaluation.

Two types of short-circuiting exist in CNF and DNF operations,inter-term short-circuiting and intra-term short-circuiting. Inter-termshort-circuiting causes the evaluation of an entire expression toevaluate to true, in the case of DNF, or false, in the case of CNF, ifany term evaluates to true or false, respectively. Intra-termshort-circuiting causes the evaluation of a conjunct or disjunct toterminate without full evaluation. In this instance, a CNF term, orconjunct, will evaluate to true if any of its sub-terms are true, whilea DNF term, or disjunct, will evaluate to false if any of its sub-termsare false. Consider the following statements:

CNF: If (A or B) and (C or D) then E,  (7)

DNF: If (A and B) or (C and D) then E.  (8)

In the CNF statement, if A evaluates to true, the entire conjunct A or Bevaluates to true. As a result, the evaluation of B is unnecessary andcan be avoided using intra-term short-circuit evaluation. From aninter-term perspective, if the conjunct A or B evaluates to false, theentire CNF expression evaluates to false, making the evaluation of theconjunct C or D superfluous. In the case of DNF, both inter andintra-term short-circuit evaluation work similarly to that of CNF,except that the term values for DNF are the converse of those for CNF.It should be noted that the Boolean processor 36 performs both inter andintra-term short-circuit evaluations, thereby providing maximumefficiency in processing expressions.

In examining the inter-term short-circuit evaluation of both CNF and DNFexpressions, the following equations can be used to characterize thebehavior of each:

Avg. CNFInstructions=((ICS*CS)+(IOS*OS))*PCSD+(ICS*CS)*(1−PCSD)*FCSD,  (9)

Avg. DNF Instructions=((ICS*CS)+IOS)*OS*(PCSD*POSD+(1−PCSD)),  (10)

where: ICS=number of processor instructions required to process acontrol state; CS=number of control states; OS=other, or non-control,states; IOS=number of processor instructions required to process an“other” state; PCSD=positive control state distribution, the probabilitythat all control states evaluate to true (e.g., a PCSD of 0.5 means thatall of the control states evaluate to true in fifty percent of theexpression evaluations); FCSD=false control state distribution, in theevent that the control states evaluate to false, this number representswhich of the control states caused the failure (e.g., a failure among 10control states with an FCSD of 0.7 means the 7^(th) control stateevaluated to false); POSD=positive “other” state distribution, theposition within the expression that an “other” state evaluates to true(e.g., a POSD of 0.5 means the 5^(th) term of 10 evaluates to true).

The following charts represent the results of varying the number ofcontrol states and “other” states in the above-referenced equations. Itshould be noted that all control states are evaluated as soon aspossible (i.e. moved as far left in the expression as possible). In thismanner, the control states are the first conjuncts in CNF equations andthe first terms in each disjunct of DNF equations. Additionally, in thecase of DNF equations, each “other” state is combined with the controlstates to form a disjunct. This results in an equal number of “other”states and disjuncts. Data is generated using a CNFDNF emulation programand complementary CNF and DNF expression classes. A fixed number ofcontrol states is entered for each run of the program. The program thenvaries the number of “other” states from zero to one-thousand, forexample. At each step, a random POSD (between 0 and 1) is used andaveraged over one-million iterations.

FIG. 5 illustrates the limited advantage of DNF. Only when theprobability for the control state to evaluate to true is one-hundredpercent, or the number of “other” states is less than two at aseventy-five percent control state probability, does DNF have anadvantage over CNF. When the control state probability is one-hundredpercent, meaning the control states are always true, and the number of“other” states becomes arbitrarily large, DNF retains its slightadvantage over CNF, as illustrated in FIG. 6. This advantage becomestrivial as the difference in number of processor instructions is minimalat this small number of states. In addition, the likelihood of aone-hundred percent probability for a control state is very remote. Forexample, in the case of a home alarm system. An alarm will sound if thesystem is armed and a door or window is opened. In this case, the systembeing armed is the control state. In a real-world application, however,an alarm system is not continuously armed. Once the number of “other”states rises above two, CNF has a distinct advantage over DNF. Thisadvantage becomes greater as the number of control states and “other”states rises, and the control state probability drops. This is apparentin FIGS. 5 through 10.

As the number of “other” states becomes arbitrarily large, the ratio ofDNF evaluations to CNF evaluations becomes relatively constant. Taking acloser look at the formulas for DNF and CNF instructions as OS becomesrelatively large and PCSD becomes relatively small, DNF becomes afunction of (OS*CS), while CNF becomes a function of (OS*PCSD). Thus,the DNF to CNF instruction ratio can be expressed as an approximatefunction of the number of control states and their positivedistribution, or hit rate, such that DNF/CNF Ratio≈CS/PCSD. Because arelatively large number of control states usually corresponds to arelatively low probability, the choice of CNF over DNF becomesadvantageous as the size of the system grows.

The combination of inter and intra-term short-circuiting provides asignificant performance gain over the use of either one alone. Assumingthat only one of x “other” states will evaluate to true during anysingle evaluation of an expression, the addition of intra-termshort-circuiting reduces the number of state evaluations by (0.5*# of“Other” States) and (0.5*# of Control States*# of “Other” States) onaverage for CNF and DNF expressions, respectively. Using both inter andintra-term short-circuiting, the above-referenced equations given todescribe the average number of instructions for both CNF and DNF become:

Avg. CNFInstructions=((ICS*CS)+(IOS*OS*POSD))*PCSD+(ICS*CS)*(1−PCSD)*FCSD,  (11)

$\begin{matrix}{{{{Avg}.\mspace{11mu} {DNF}}\mspace{14mu} {Instructions}} = {\left( {\left( {{{ICS}*{CS}} + {IOS}} \right)*{OS}*{PCSD}*{POSD}} \right) + \left( {\left( {{{ICS}*{{CS8}\left( {1 - {PCSD}} \right)}*{FCSD}} + {IOS}} \right)*{{OS}.}} \right.}} & (12)\end{matrix}$

FIGS. 11 through 14 illustrate the DNF/CNF ratio for 1 and 10 controlstates, each combined with small and large numbers of “other” states.

Using inter and intra-term short-circuiting together ultimately resultsin the identical DNF/CNF ratio (for large “other” states) as when usingonly inter-term short-circuiting. However, the number of averageevaluations for each of the two Boolean forms is reduced by fiftypercent. Prior to reaching the ratio limit, the effect of using bothtypes of short-circuiting on DNF is especially prevalent, as illustratedby the reduction of the slope of the curve of FIG. 14 as compared withits inter-term short-circuiting counterpart of FIG. 10.

Thus, short-circuiting provides a performance gain by reducing thenumber of instructions evaluated by the Boolean processor 36 (FIGS. 3and 4). The actual gain is a function of the number of control states,the number of “other” states, the number of instructions for each, andthe positive distribution of each. Using the above-referenced equationfor the average CNF evaluations for inter and intra-term shortcircuiting:

Avg. CNFInstructions=((ICS*CS)+(IOS*OS*POSD))*PCSD+(ICS*CS)*(1−PCSD)*FCSD,  (13)

and the following formula for the number of evaluations fornon-short-circuited CNF:

CNF Instructions=(ICS*CS)+(IOS*OS),  (14)

the improvement that short-circuiting provides can be evaluated, asillustrated in Table 1.

TABLE 1 Percentage of Instructions Saved Using CNF Short-CircuitedEvaluation Instead of Non-Short-Circuited Evaluation Average PositivePositive Short-Circuit % Savings Control “Other” Control “Other”Evaluations Non-Short-Circuit Using States States State DistributionState Distribution (FCSD = 0.5) Evaluations Short-Circuiting 1 5 1 0.53.5 6 41.67% 1 10 1 0.5 6 11 45.45% 1 10 0.5 0.5 3.25 11 70.45% 1 100.25 0.5 1.875 11 82.95% 1 10 0.1 0.5 1.05 11 90.45% 1 100 1 0.5 51 10149.50% 1 100 0.5 0.5 25.75 101 74.50% 1 100 0.25 0.5 13.125 101 87.00% 1100 0.1 0.5 5.55 101 94.50% 1 1000 1 0.5 501 1001 49.95% 1 1000 0.5 0.5250.75 1001 74.95% 1 1000 0.25 0.5 125.625 1001 87.45% 1 1000 0.1 0.550.55 1001 94.95% 5 5 1 0.5 7.5 10 25.00% 5 10 1 0.5 10 15 33.33% 5 100.5 0.5 6.25 15 58.33% 5 10 0.25 0.5 4.375 15 70.83% 5 10 0.1 0.5 3.2515 78.33% 5 100 1 0.5 55 105 47.62% 5 100 0.5 0.5 28.75 105 72.62% 5 1000.25 0.5 15.625 105 85.12% 5 100 0.1 0.5 7.75 105 92.62% 5 1000 1 0.5505 1005 49.75% 5 1000 0.5 0.5 253.75 1005 74.75% 5 1000 0.25 0.5128.125 1005 87.25% 5 1000 0.1 0.5 52.75 1005 94.75% 10 10 1 0.5 15 2025.00% 10 20 1 0.5 20 30 33.33% 10 10 0.5 0.5 10 20 50.00% 10 10 0.250.5 7.5 20 62.50% 10 10 0.1 0.5 6 20 70.00% 10 100 1 0.5 60 110 45.45%10 100 0.5 0.5 32.5 110 70.45% 10 100 0.25 0.5 18.75 110 82.95% 10 1000.1 0.5 10.5 110 90.45% 10 1000 1 0.5 510 1010 49.50% 10 1000 0.5 0.5257.5 1010 74.50% 10 1000 0.25 0.5 131.25 1010 87.00% 10 1000 0.1 0.555.5 1010 94.50%

Because the number of instructions required to evaluate a control stateis typically the same as the number required to evaluate “other” states,one instruction is assumed for each. The savings illustrated in theTable 1 range from twenty-five to almost ninety-five percent. While thehigh-end of this range represents a typical system, in terms of thenumber of control states versus “other” states, the low-end of the rangeoccurs when the number of control states is equal to or near the numberof “other” states. In a typical configuration, the number of “other”states outweighs the number of control states, resulting in a relativelyhigher instruction evaluation savings. In light of all of the above, theuse of CNF outweighs any benefit provided by DNF, thereby warranting anarchitectural design that uses Boolean expressions compiled into CNF.

As described above, the Boolean processor 36 (FIGS. 3 and 4) is ageneral-purpose architecture that is intended to monitor and control itssurrounding environment. The small instruction set and design of theBoolean processor 36 are intended to give it a significant speedadvantage over its competition, namely other general-purposearchitectures, such as microprocessors and microcontrollers. Todemonstrate this advantage, the instruction set of the Boolean processor36 is compared with the instruction sets of two other general-purposearchitectures; the Intel 8051 microcontroller and the Intel 8088 familyof microprocessors. In addition, the Motorola MMC2107 microcontroller isused for comparison purposes.

Like other microcontrollers, the main purpose of the 8051 is to controlits surrounding environment. Because the 8051 is not optimized forBoolean operations, it requires the use of several instructions in orderto emulate the functions of the Boolean processor 36 of the presentinvention. In addition, it also requires the use of two registers: oneregister to hold the intermediate results of OR calculations and anotherregister for retrieving device states from memory. AND calculationsresulting in a false value can be handled by issuing a jump past theoperation that results from a true evaluation of the statement. Theinstructions required to perform the same operations as those of theBoolean processor 36 are illustrated in Table 2. It should be noted thatthe label SHORT is the label for the instruction immediately followingthe current CNF expression and is used for inter-term short-circuiting.The SHORTCON label is the label for the next OR term of a conjunct andis used for intra-term short-circuiting.

TABLE 2 Intel 8051 Equivalent Instructions Boolean Processor 8051Equivalent Instruction Instruction(s) Explanation AND MOV Rr, add Movethe state of the device at add into register Rr, CJNE Rr, #n, SHORT Ifthe value in Rr is not equal to the state specified in #n, then theexpression is false and may be short circuited. OR MOV Rr, add Move thestate of the device at add into register Rr. CJNE Rn, #n, NEXT If thevalue in Rr is not equal to the state specified MOV Rx, #1 in #n, we setRx to 0 and move on to the next OR SJMP SHORTCON term or the nextconjunct. If it is equal, we set the NEXT MOV Rx, #0 value of Rx to 1and short circuit the remainder of the conjunct. Rx will be used at theend of operation to determine the final outcome of the entire CNFexpression. End of Operation CJNE Rx, #1, SHORT If Rx does not equalone, then one of the conjuncts MOV #n, add containing OR terms did notevaluate to true. Therefore, the entire expression is false. If Rx isequal to one, the expression is true and the resulting state change maybe made to the device at add. No Operation NOP PC = PC + 1 UnconditionalSJMP radd Jump to the line specified by radd. Jump Conditional Jump CJNERn, #n, radd If the value in Rn is not equal to #n, then jump to theline specified by radd. Start of Operation MOV Rx, #1 Move 1 intoregister Rx which is used to hold the result value of conjunctscontaining OR terms. Start of OR MOV Rx, #1 See Start of Operation.Conjunct — CJNE Rx, #1, SHORT This operation is required at the end ofan OR Conjunct. If the value of Rx is not equal to 1, the value of theconjunct and, hence, the value of the entire expression is false and maybe short- circuited.

EXAMPLE 5

The statement: If dev1=1 and dev2=3 and (dev3=1 or dev4=2) then dev6=8,is written for the Intel 8051 as follows:

BEGIN: MOV R1, #1 Initialize R1 to 1 (OR holder) MOV R0, dev1 Move stateof device 1 into R0 CJNE R0, #1, SHORT If dev1 not = to 1 then gotoSHORT MOV R0, dev2 Move state of device 2 into R0 CJNE R0, #3, SHORT Ifdev2 not = to 3 then goto SHORT MOV R0, dev3 Move state of device 3 intoR0 CJNE R0, #1, NEXT If dev3 not = to 1 then goto NEXT MOV R1, #1 Iftrue set R1 to 1 SJMP SHORTCON Jump to end of OR conjunct NEXT: MOV R1,#0 If false set R1 to 0 MOV R0, dev4 Move state of device 4 into R0 CJNER0, #2, NEXT2 If dev4 not = to 2 then goto NEXT2 MOV R1, #1 If true setR1 to 1 SJMP SHORTCON Jump to end of OR conjunct NEXT2: MOV R1, #0 Iffalse set R1 to 0 SHORTCON: CJNE R1, #1, SHORT If OR Holder not = 1 thengoto SHORT MOV #8, dev6 Expression is true, set dev6 = 8 SHORT: NOP NoOperation or start of next if then block SJMP BEGIN Start again and keeptesting

The same statement is implemented for the Boolean processor 36 using thefollowing code:

Control Store Instruction Register Address Address Control/State OpcodeFunctionality 00000000 00000011 00000000 110 Start of Boolean expr.00000001 00000001 00000001 000 Dev1 = 1? (AND) 00000010 0000001000000011 000 Dev2 = 3? (AND) 00000011 00000110 00000000 111 Start of ORconjunct 00000100 00000011 00000001 001 Dev3 = 1? (OR) 00000101 0000010000000010 001 Dev3 = 1? (OR) 00000110 00000110 00001000 010 End ofOperation 00000111 00000000 00000000 100 Jump to beginning

What required eighteen instructions using the 8051, required only eightinstructions using the Boolean processor 36. Using the differences inthe number of instructions required for each operation, the extra numberof instructions required to emulate the functionality of the Booleanprocessor 36 for an 8051 can be measured as such:

Extra Instructions=D-And*CS+D-Or*OS+OC+D-EoO,  (15)

where: D-And=difference in number of instructions for an Andoperation=1; CS=number of control states; D-Or=difference in number ofinstructions for an Or Operation=4; OS=number of “other” states;OC=number of OR conjuncts; and D-EoO=difference in number ofinstructions for an End of Operation=1. Simplified, the resultingequation is:

Extra Instructions=CS+4OS+OC+1.  (16)

The two jump codes, the two start codes, and the no-op code are notincluded in the calculation because they all require one instruction oneach architecture and would, therefore, cancel out with a difference ofzero. The number of OR conjuncts is taken into account since the 8051requires an extra instruction to handle each one. Assuming, that as thesize of system grows, the number of “other” states grows exponentiallyrelative to the number of control states and the number of OR conjuncts;the number of extra instructions becomes a linear function such that:Extra Instructions=4OS. This difference becomes significant as thenumber of “other” states becomes relatively large, as illustrated inFIG. 15.

The Intel 8086 family of microprocessors includes upward-compatibilitywhich allows code written for previous-generation chips to be run on itsancestors. The 8086 family includes the 8086, 80186, 80286, 80386,80486, and the Pentium models, each offering enhancements to that of itspredecessor in terms of performance, memory management, and, in somecases, instruction sets. The basic jump, test, and move instructionsrequired to emulate the functionality of the Boolean processor 36 arepart of each of the processor's basic instruction set and can be used torepresent the entire family. Being general-purpose platforms, the Intelmicroprocessors, like the 8051, are not optimized for Booleanoperations. As a result, they also require the use of two registers forholding the results of OR operations and for storing states retrievedfrom memory. The instructions required to perform the same operations asthose of the Boolean processor are illustrated in Table 3.

TABLE 3 Intel 8086 Family of Microprocessors Equivalent InstructionsBoolean Processor 8086 Family Equivalent Instruction Instruction(s)Explanation AND MOV Rr, add Move the state of the device at add intoregister Rr, If CMP Rr, #n the value in Rr is not equal to the statespecified in JNE SHORT #n, then the expression is false and may be shortcircuited. OR MOV Rr, add Move the state of the device at add intoregister Rr. If CMP Rn, #n the value in Rr is not equal to the statespecified in JNE NEXT #n, we set Rx to 0 and move on to the next OR termMOV Rx, #1 or the next conjunct. If it is equal, we set the value of JMPSHORTCON Rx to 1 and short circuit the remainder of the NEXT MOV Rx, #0conjunct. Rx will be used at the end of operation to determine the finaloutcome of the entire CNF expression. End of CMP Rx, #1 If Rx does notequal one, then one of the conjuncts Operation JNE SHORT containing ORterms did not evaluate to true. MOV #n, add Therefore, the entireexpression is false. If Rx is equal to one, the expression is true andthe resulting state change may be made to the device at add. NoOperation NOP PC = PC + 1 Unconditional SJMP radd Jump to the linespecified by radd. Jump Conditional CMP Rn, #n If the value in Rn is notequal to #n, then jump to the Jump JNE radd line specified by radd.Start of MOV Rx, #1 Move 1 into register Rx which is used to hold theOperation result value of conjuncts containing OR terms. Start of OR MOVRx, #1 See Start of Operation. Conjunct — CMP Rx, #1 This operation isrequired at the end of an OR JNE SHORT Conjunct. If the value of Rx isnot equal to 1, the value of the conjunct and, hence, the value of theentire expression is false and may be short-circuited.

EXAMPLE 6

The statement given in the previous Intel 8051 example: If dev1=1 anddev2=3 and (dev3=1 or dev4=2) then dev6=8, would be written for an 8086processor as follows:

BEGIN: MOV R1, #1 Initialize R1 to 1 (OR holder) MOV R0, dev1 Move stateof device 1 into R0 CMP R0, #1 Compare dev1 state to 1 JNE SHORT If dev1not = to 1 then goto SHORT MOV R0, dev2 Move state of device 2 into R0CMP R0, #3 Compare dev2 state to 3 JNE SHORT If dev2 not = to 3 thengoto SHORT MOV R0, dev3 Move state of device 3 into R0 CMP R0, #1Compare dev3 state to 1 JNE NEXT If dev3 not = to 1 then goto NEXT MOVR1, #1 If true set R1 to 1 JMP SHORTCON Jump to end of OR conjunct NEXT:MOV R1, #0 If false set R1 to 0 MOV R0, dev4 Move state of device 4 intoR0 CMP R0, #2 Compare dev4 state to 2 JNE NEXT2 If dev4 not = to 2 thengoto NEXT2 MOV R1, #1 If true set R1 to 1 JMP SHORTCON Jump to end of ORconjunct NEXT2: MOV R1, #0 If false set R1 to 0 SHORTCON: CMP R1, #1Compare OR Holder to 1 JNE SHORT If OR Holder not = 1 then goto SHORTMOV #8, dev6 Expression is true, set dev6 = 8 SHORT: NOP No Operation orstart of next if then block JMP BEGIN Start again and keep testing

In the above-referenced example, the 8086 family requires twenty-fourinstructions to execute the same functionality that only requires eightinstructions for the Boolean processor 36. Using the differences in thenumber of instructions required for each operation, the extra number ofinstructions required to emulate the functionality of the Booleanprocessor 36 for the 8086 can be measured as such:

Extra Instructions=D-And*CS+D-Or*OS+CJ+D-OC*OC+D-EoO,  (17)

where: D-And=difference in number of instructions for an Andoperation=1; CS=number of control states; D-Or=difference in number ofinstructions for an Or Operation=4; OS=number of “other” states;CJ=number of conditional jumps (difference=1); D-OC=difference in numberof instructions for an Or Conjunct=2; OC=number of OR conjuncts; andD-EoO=difference in number of instructions for an End of Operation.Simplified, the resulting equation is:

Extra Instructions=2CS+5OS+CJ+2OC+2.  (18)

The unconditional jump code, the two start codes, and the no-op code arenot included in the calculation because they all require one instructionfor each architecture and would, therefore, cancel out with a differenceof zero. Assuming that as the size of system grows, the number of“other” states grows exponentially relative to the number of controlstates and the number of OR conjuncts, the number of extra instructionsbecomes a linear function such that: Extra Instructions=5OS, asillustrated in FIG. 16.

The Motorola MMC2107 is a microcontroller that is designed to meet theneeds of distribution channel customers dealing with applications, suchas vending machines, building management and heating-ventilation-airconditioning (HVAC) systems, exercise equipment and lighting control.Similar to the comparisons of the Boolean processor 36 to the 8051 and8086 family, the emulation of the Boolean processor 36 by the MMC2107requires the use of two registers for holding the results of ORoperations and for storing states retrieved from memory. Theinstructions required to perform the same operations as those of theBoolean processor 36 are illustrated in Table 4.

TABLE 4 Motorola MMC2107 Equivalent Instructions Boolean MotorolaMMC2107 Processor Equivalent Instruction Instruction(s) Explanation ANDLDB Rr, add Load the state of the device at add into register Rr, If theCMPNEI Rr, imm5 value in Rr is not equal to the state specified in imm5,BT SHORT then the expression is false and may be short circuited. (Thisis used for up to 32 states). -or- LDB Rr, add Load the state of thedevice at add into register Rr, Put MOVI Rn, imm7 the value of the statebeing compared in Rn. If the value CMPNE Rr, Rn in Rr is not equal tothe state in Rn, then the expression BT SHORT is false and may be shortcircuited. (This is used for up to 128 states). -or- LDB Rr, add Loadthe state of the device at add into register Rr, Put MOVI Rn, imm7 thevalue of the state being compared in Rn. In order to LSLI Rn, imm5compare Rr to a number greater than 127, the value must ADDI Rn, oimm5be loaded into Rn via a series of Logical Left Shifts and CMPNE Rr, RnAdds. If the value in Rr is not equal to the state in Rn, BT SHORT thenthe expression is false and may be short circuited. (This is used forstates >128). OR LDB Rr, add Move the state of the device at add intoregister Rr. If CMPNEI Rn, imm5 the value in Rr is not equal to thestate specified in BT NEXT imm5, we set Rx to 0 and move on to the nextOR term MOVI Rx, 1 or the next conjunct. If it is equal, we set thevalue of JMPI SHORTCON Rx to 1 and short circuit the remainder of theconjunct. NEXT MOVI Rx, 0 Rx will be used at the end of operation todetermine the final outcome of the entire CNF expression. (This block isused for up to 32 states.) -or- LDB Rr, add Move the state of the deviceat add into register Rr. MOVI Rn, imm7 Load the comparison value intoRn. If the value in Rr is CMPNE Rr, Rn not equal to Rn, we set Rx to 0and move on to the next BT NEXT OR term or the next conjunct. If it isequal, we set the MOVI Rx, 1 value of Rx to 1 and short circuit theremainder of the JMPI SHORTCON conjunct. Rx will be used at the end ofoperation to NEXT MOVI Rx, 0 determine the final outcome of the entireCNF expression. (This block is used for up to 128 states.) -or- LDB Rr,add Move the state of the device at add into register Rr. MOVI Rn, imm7Load the comparison value into Rn. In order to compare LSLI Rn, imm5 Rrto a number greater than 127, the value must be ADDI Rn, oimm5 loadedinto Rn via a series of Logical Left Shifts and CMPNE Rr, Rn Adds. Ifthe value in Rr is not equal to Rn, we set Rx to BT NEXT 0 and move onto the next OR term or the next conjunct. MOVI Rx, 1 If it is equal, weset the value of Rx to 1 and short circuit JMPI SHORTCON the remainderof the conjunct. Rx will be used at the NEXT MOVI Rx, 0 end of operationto determine the final outcome of the entire CNF expression. (This blockis used for >128 states.) End of CMPNEI Rx, 1 If Rx does not equal one,then one of the conjuncts Operation BT SHORT containing OR terms did notevaluate to true. Therefore, MOVI Rn, imm7 the entire expression isfalse. If Rx is equal to one, the STB Rn, add expression is true and theresulting state change may be made to the device at add. (This block isused for up to 128 state values.) -or- CMPNEI Rx, 1 If Rx does not equalone, then one of the conjuncts BT SHORT containing OR terms did notevaluate to true. Therefore, MOVI Rn, imm7 the entire expression isfalse. If Rx is equal to one, the LSLI Rn, imm5 expression is true andthe resulting state change may be ADDI Rn, oimm5 made to the device atadd. In order to make a state STB Rn, add change to a value higher than127, the value must be loaded into Rn via a series of Logical LeftShifts and Adds. (This block is used for >128 state values.) NoOperation ADDI PC, 1 Increment the program counter by 1. PC = PC + 1Unconditional JMPI radd Jump to the line specified by radd. JumpConditional CMPNEI Rr, imm5 If the value in Rr is not equal to imm5,then jump to the Jump BT radd line specified by radd. (This block isused for comparison with values up to 32). -or- MOVI Rr, imm7 Place thecomparison state value in Rn. If the value in CMPNE Rr, Rn Rr is notequal to the value in Rn, then jump to the line BT radd specified byradd. (This block is used for comparison with values up to 127). -or-MOVI Rn, imm7 Place the comparison state value in Rn.. In order to LSLIRn, imm5 load Rn with a value higher than 127, the value must be ADDIRn, oimm5 loaded into Rn via a series of Logical Left Shifts and CMPNERr, Rn Adds. If the value in Rr is not equal to the value in Rn, BT raddthen jump to the line specified by radd. (This block is used forcomparison with values >127). Start of MOVI Rx, 1 Move 1 into registerRx which is used to hold the result Operation value of conjunctscontaining OR terms. Start of OR MOVI Rx, 1 See Start of Operation.Conjunct — CMPNEI Rx, 1 This operation is required at the end of an ORConjunct. BT SHORT If the value of Rx is not equal to 1, the value ofthe conjunct and, hence, the value of the entire expression is false andmay be short-circuited.

EXAMPLE 7

The statement given in the previous 8051 and 8086 family examples: Ifdev1=1 and dev2=3 and (dev3=1 or dev4=2) then dev6=8, would be writtenfor the MMC2107 as follows:

BEGIN: MOVI R1, 1 Initialize R1 to 1 (OR holder) LDB R0, dev1 Move stateof device 1 into R0 CMPNEI R0, 1 Compare dev1 state to 1 BT SHORT Ifdev1 not = to 1 then goto SHORT LDB R0, dev2 Move state of device 2 intoR0 CMPNEI R0, 3 Compare dev2 state to 3 BT SHORT If dev2 not = to 3 thengoto SHORT LDB R0, dev3 Move state of device 3 into R0 CMPNEI R0, 1Compare dev3 state to 1 BT NEXT If dev3 not = to 1 then goto NEXT MOVIR1, 1 If true set R1 to 1 JMPI SHORTCON Jump to end of OR conjunct NEXT:MOVI R1, 0 If false set R1 to 0 LDB R0, dev4 Move state of device 4 intoR0 CMPNEI R0, 2 Compare dev4 state to 2 BT NEXT2 If dev4 not = to 2 thengoto NEXT2 MOVI R1, 1 If true set R1 to 1 JMPI SHORTCON Jump to end ofOR conjunct NEXT2: MOVI R1, #0 If false set R1 to 0 SHORTCON: CMPNEI R1,1 Compare OR Holder to 1 BT SHORT If OR Holder not = 1 then goto SHORTMOVI R0, 8 Expression is true, set dev6 = 8 STB R0, dev6 SHORT: NOP NoOperation or start of next if then block JMP BEGIN Start again and keeptesting

In the above-referenced example, the MMC2107 requires twenty-fiveinstructions to execute the same functionality that only requires eightinstructions for the Boolean processor 36. It should also be noted thatthe MMC2107's MCORE™ instruction set requires the use of additionalinstructions for loading and comparing values greater than thirty-two(see the “Explanation” column of Table 4). Using the differences in thenumber of instructions required for each operation, the extra number ofinstructions required to emulate the functionality of the Booleanprocessor 36 for a Motorola MMC2107 can be measured as such:

Extra Instructions=D-And*CS+D-Or*OS+CJ+D-OC*OC+D-EoO,  (19)

where: D-And=difference in number of instructions for an And operation;CS=number of control states; D-Or=difference in number of instructionsfor an Or Operation; OS=number of “other” states; CJ=number ofconditional jumps; D-OC=difference in number of instructions for an OrConjunct; OC=number of OR conjuncts; and D-EoO=difference in number ofinstructions for an End of Operation. Simplified, the resultingequations are:

$\begin{matrix}{{{{Extra}\mspace{14mu} {Instructions}} = {{2{CS}} + {5{OS}} + {CJ} + {20C} + {3\left( {{for} < {32\mspace{14mu} {states}}} \right)}}},} & (20) \\{{{{Extra}\mspace{14mu} {Instructions}} = {{3{CS}} + {6{OS}} + {2{CJ}} + {20C} + {3\left( {{for}<={128\mspace{14mu} {states}}} \right)}}},{and}} & (21) \\{{{Extra}\mspace{14mu} {Instructions}} = {{5{CS}} + {8{OS}} + {4{CJ}} + {20C} + {5{\left( {{for} > {128\mspace{14mu} {states}}} \right).}}}} & (22)\end{matrix}$

The unconditional jump code, the two start codes, and the no-op code arenot included in the calculation because they all require one instructionon each architecture and would, therefore, cancel out with a differenceof zero. Assuming, that as the size of system grows, the number of“other” states grows exponentially relative to the number of controlstates and the number of OR conjuncts, the number of extra instructionsbecomes a series of linear functions such that:

Extra Instructions=5OS (for <32 states),  (23)

Extra Instructions=6OS (for <=128 states), and  (24)

Extra Instructions=8OS* (for >128 states).  (25)

*(These values could change depending upon the size of the values beingloaded and compared)

These functions are illustrated in FIG. 17.

An exemplary application for the Boolean processor 36 (FIGS. 3 and 4) isto manage the state of a set of devices, where the state of one or moredevices may necessitate a change in one or more other devices. Anexample is a home alarm system: “If a door or window is opened while thesystem is armed, sound an alarm”. The architecture provides a mechanismfor a device to report information about itself, that is, its stateinformation, and also a mechanism for changing the state of any deviceattached to the system. For example, a home automation and alarm systemcould constantly monitor the state of any number of devices in a house;from doors and windows, to lamps, to televisions, to VCRs. It provides ameans for checking the open/closed status of doors and windows, checkingwhether or not an electrical device is on or off, and also changing thestate of the devices (e.g., change the TV channel or turn a lamp on).

Another exemplary use for the Boolean processor 36 is for automobileautomation. For example, a proximity sensor could be attached to a car.It is responsible for sensing how close the car is to an object. If thedistance between the car and the object closes to within a predetermineddistance, the proximity sensor reports a state of ‘too close’ to theBoolean processor 36. The Boolean processor 36 recognizes this state andinitiates a state change to the brake system, thereby slowing the caruntil a safe distance is achieved.

As described above, the Boolean processor 36 is designed for monitoringand automation applications ranging from small to large-scale. Theseapplications can range from home automation and alarm systems toaeronautical and automobile control systems. The Boolean processor 36 iscapable of monitoring any type of device provided that the device meetsthe following criteria: it is capable of receiving an n-bit address fromthe processor 36 (this address is used by both the device and theprocessor 36 to recognize state reporting and enable state changes); itis capable of recognizing its address and reporting its state in anm-bit word, where m is the word size of the device stage storage unit(RAM) 64; and it is capable of recognizing its address and changing itsoperating state on demand. While the outbound portion of thecommunications between the processor 36 and the devices it controls isachieved via a direct connection, the inbound portion is achieved by acomplementary architecture that polls devices for their states and loadsthe states in the RAM 64 of the processor 36. In order to meet the abovelisted requirements for using the processor 36 in practicalapplications, two complementary architectures have been designed: adevice polling unit and a device interface unit.

Referring to FIG. 18, the device polling unit 66 functions as the maininterface between the peripheral devices and the RAM 64. The devicepolling unit 66 is responsible for finding new devices, assigning deviceaddresses, polling the devices for their current states, and updatingthe RAM 64 with those states. The device polling unit 66 includes amaximum device address electrically-erasable programmable read-onlymemory (EEPROM) 68, which stores the highest address of all knowndevices on the system. The maximum device address EEPROM 68 has anincrement line, which increments its value by one whenever it isasserted. It also has n output lines, which constantly output its value.Its value is incremented when a new device is added to the system viathe assertion of the new device found line. The device polling unit 66also includes an n-bit incrementing register 70, which holds an n-bitnumber representing the current address of the device being polled. Ithas a reset line, which sets the register to zero when asserted. It alsohas an increment line and n output lines, which constantly output itsvalue to an AND unit 72 and a current address encoder 74. If a newdevice is not found on the system, the negation of the new device foundline asserts the increment line on the register, enabling it to cyclethrough and poll all of the attached devices by address. The devicepolling unit 66 includes two AND units 72. One unit allows the value ofthe maximum device address EEPROM 68 to be sent to a new address encoder76 if the new address line has been asserted (i.e. a new device has beendetected). The second AND unit 72 is used to reset the incrementingregister 70 if it equals the maximum device address. The latter is usedto conserve clock cycles. Without it, the register would reset uponoverflow. In its absence, however, the design would work with n devices;it saves 2^(n)-(# of attached devices) clock cycles each time it pollsall of the attached devices. The device polling unit 66 includes twoaddress encoders. These units are designed to take n bits in paralleland output them serially. One encodes new addresses, while the otherencodes the address of the device being polled. The device polling unit66 further includes a device address and state decoder 78, which acceptsserial input in blocks of n+m bits, representing the device address andthe state of the device, respectively, and outputs them in parallel tothe RAM 64. It should be noted that the encoder and decoder are notmandatory, and are only required in the case that a serial bus device isused.

The device polling unit 66 operates in a continuous loop after it isstarted. First, it checks for new devices added to the system. If a newdevice is found (the new device found line is asserted), the devicepolling unit 66 assigns a system address to it. If a new device is notpresent in the system, the n-bit incrementing register 70 isincremented, the device polling unit 66 polls the device correspondingto the address in the incrementing register 70, and then copies thedevice's current state into the RAM 64. The loop is then repeated. Oncethe device polling unit 66 is running, it continues to loop, polling fornew devices and retrieving device states.

The device polling unit 66 finds new devices by clocking (asserting) thenew device seek line. If a new device exists, the new device found lineis asserted, incrementing the maximum device address EEPROM 68 andactivating the AND gate 72, which allows the address to pass into thenew address encoder 76.

Device polling is achieved via the incrementing register 70, whichconstantly outputs its value to the current address encoder 74. It loopsthrough all of the device addresses. The end of the series of devices isrecognized when the current device address reaches the maximum deviceaddress. This is determined when the result of the current deviceaddress AND's with the maximum device address EEPROM's value, resettingthe incrementing register 70 to zero. For each address, the devicepolling unit 66 asserts the state enable line, requesting the device'sstate. When a device detects its address on the state enable line, itoutputs (e.g., serially) its address and state on the device state line.The device address and state decoder 78 then outputs the n+m bits(representing the device address and state, respectively) to the RAM 64.

Referring to FIG. 19, each device that interfaces with the Booleanprocessor 36 (FIGS. 3 and 4) is assumed to be a relatively intelligentdevice that can accept an n-bit address and has up to m states.Accordingly, the device interface unit 80 includes a new device EEPROM82, which is a 1-bit store that is set to one when the device is built.When the new device seek line is asserted, this bit (on a new device)will assert the new device found line. The device interface unit 80 alsoincludes an address decoder 84. If the new device EEPROM bit is set, itwill allow the address passed on the new address line to be placed inthe n-bit address EEPROM 86 and then clear the new device EEPROM 82.Once the new device EEPROM 82 has been cleared, it will only passaddresses to the AND gate 72 that tests to see if the device is beingasked for its state. The device interface unit 80 further includes acontrol word decoder 88, which reads the serial bits off of the controlline. If the address matches the address in the address EEPROM, thecontrol bits output to the device controller to change its state. It isreset via internal logic that counts the assertion of the new deviceseek line and resets every n+m clock cycles. The device interface unit80 further includes the n-bit address EEPROM 86, which stores theaddress of the device and constantly outputs it, an m-bit state register90, which holds the current state of the device and has an output enableline that allows it to output its value, and an address encoder 92,which accepts an n-bit address and an m-bit state and outputs them(e.g., serially) on the device state line.

The device interface unit 80 is designed to listen for the followingassertions: New Device Seek, New Address, State Enable, and ControlLine. The unit determines whether or not it has any work to do as aresult of any such assertion. If so, it may assert any of the followingback to the caller: New Device Found and Current State of the Device.When a device is attached to the bus, its value for the new deviceEEPROM 82 is set to ‘1’. This indicates that it has not yet beenincorporated into the system. When the new device seek line is asserted,its value (‘1’) is passed to an AND gate 72 along with the value (‘1’)for the new device EEPROM 82. If it is a new device, i.e. the result ofthe AND is ‘1’, the new device found line is asserted, informing thedevice polling unit 66 of the existence of a new device.

By default, the device interface unit 80 “listens” for a new address onthe new address line. The assertion of the new device found line forcesthe device polling unit 66 to return the next device address. The newaddress is placed in the n-bit address EEPROM 86. The address decoder 84then clears the new device EEPROM 82. The next time the device receivesthe new device seek line assertion, it does not assert the new deviceline. The device has now been assimilated. Once assimilated, the devicemay be polled for its state. During the polling phase of the devicepolling unit 66, each device is queried by its address. When queried,the device interface unit 80 recognizes its address and returns itscurrent state. When the state enable line is asserted to the device, theaddress decoder 84 compares the address on the line with the deviceaddress stored in the address EEPROM 86. This comparison is performedvia an AND gate 72. If the addresses match, then the request for stateinformation is directed to this device. The positive result of the ANDcauses the output enable line to the state register to be asserted andthe address/state encoder 92 to be enabled. The state information issent to the address/state encoder 92. The address/state encoder 92accepts the n-bit address and the m-bit state and outputs them seriallyor in parallel on the device state line(s).

If the Boolean processor 36 detects a combination of states thatrequires a change in another state, it will send the information overthe control line. Each device interface unit accepts and reads the datafrom the asserted control line. The control word decoder 88 compares theincoming address to the address in the address EEPROM 86. If theaddresses match, the request to make a state change is made to thecurrent device. The control bits are then output to the devicecontroller to initiate a change to its state.

Referring to FIGS. 20 and 21, one of the advantages of having a systemincluding the Boolean processor 36, the device polling unit 66, and aplurality of devices 94 is that the slowest operation of the system,namely the polling of devices, is decoupled from the processingperformed by the Boolean processor 36. This allows the Boolean processor36 to run at full speed, unencumbered by the relative speed of thedevice polling unit 66 and the device bus.

An exemplary Boolean processor-based system is a home automation/alarmsystem. The Boolean processor 36 monitors and controls, for example, 256devices (n 8), each device having, for example, 256 states (m=8). Thesystem includes, for example, a door, a window, a lamp, and a motiondetector. In addition to these units, the system uses a clock, anarm/disarm unit, and a siren. Although the majority of possible devicestates and control words are not used in this example, the full eightbits for addressing, state reporting, and state changes are used. Eachdevice functions as follows:

EXAMPLE 8

Door Sensor States 8-bit value (System Address = 00000001) Open 00000000Closed 00000001 Window Sensor States 8-bit value (System Address =00000010) Open 00000000 Closed 00000001 Motion Detector States 8-bitvalue (System Address = 00000011) No Motion 00000000 MotionOccurring00000001 Lamp (System Address = 00000100) States 8-bit value Off00000000 On 00000001 Control Functions 8-bit value Turn Off 00000000Turn On 00000001 Flash 00000010 Stop Flashing 00000011 (return topre-flash state) Clock (System Address = 00000101) States 8-bit valueGet Current Time Value corresponds to 10 minute increments from 00:00.(Ex: 12:30 am = 00000011; 10:10 am = 00111101) Arm/Disarm Unit States8-bit value (System Address = 00000110) System Disarmed 00000000 SystemArmed 00000001 Control Functions 8-bit value Disarm System 00000000 ArmSystem 00000001 Siren (System Address = 00000111) States 8-bit value Off00000000 On 00000001

In addition to the above assumptions, it is assumed that a personalcomputer (PC) is interfaced with the system and is used to translatecode into micro-code and to load the control store. The homeautomation/alarm system functions as follows: At 6:00 am, disarm thealarm system; At 8:30 am, arm the alarm system; At 5:00 pm, disarm thealarm system; At 5:30 pm, turn the lamp on; At 10:30 pm, arm the alarmsystem; and At 10:30 pm, turn the lamp off.

If the alarm system is armed and the door or window is open, the sirensounds and the light flashes until the alarm system is disarmed. Thehigh-level code entered into the PC is as follows:

10: if time = 6am then arm/disarm = disarm; if time = 8:30am thenarm/disarm = arm; if time = 5pm then arm/disarm = disarm; if time =5:30pm then lamp = on; if time = 10:30pm then arm/disarm = arm; if time= 10:30pm then lamp = off; if arm/disarm = armed and (door = open orwindow = open) then  while arm/disarm = armed   siren = on;   lamp =flash;  end while; goto 10;

The compiled micro-program for this functionality is illustrated inTable 5.

TABLE 5 Home Automation/Alarm System Micro-program Control InstructionRegister Store Control/ Address Address State Opcode Functionality00000000 00000011 00000000 110 Start of Boolean expr. 00000001 0000010100100100 000 Time = 6 am? (AND) 00000010 00000110 00000000 010 Disarmsystem if TRUE. 00000011 00000110 00000000 110 Start of Boolean expr.00000100 00000101 00110011 000 Time = 8:30 am? (AND) 00000101 0000011000000001 010 Arm system if TRUE 00000110 00001001 00000000 110 Start ofBoolean expr. 00000111 00000101 01100110 000 Time = 5 pm? (AND) 0000100000000110 00000000 010 Disarm system if TRUE 00001001 00001100 00000000110 Start of Boolean expr. 00001010 00000101 01101001 000 Time = 5:30pm? (AND) 00001011 00000100 00000001 010 Turn lamp on if TRUE 0000110000001111 00000000 110 Start of Boolean expr. 00001101 00000101 10000111000 Time = 10:30 pm? (AND) 00001110 00000110 00000001 010 Arm System ifTRUE 00001111 00010010 00000000 110 Start of Boolean expr. 0001000100000101 10000111 000 Time = 10:30 pm? (AND) 00010001 00000100 00000000010 Turn lamp off if TRUE 00010010 00011001 00000000 110 Start ofBoolean expr. 00010011 00000110 00000001 000 System Armed? (AND)00010100 00010111 00000000 111 Start of Conjunct 00010101 0000000100000000 001 Door Open? (OR) 00010110 00000010 00000000 001 Window Open?(OR) 00010111 00000111 00000001 010 Turn Siren on if TRUE 0001100000000100 00000010 010 Flash lamp if TRUE 00011001 00011101 00000000 110Start of Boolean expr. 00011010 00000110 00000000 000 System Disarmed?(AND) 00011011 00000111 00000000 010 Turn siren off 00011100 0000010000000011 010 Stop flashing lamp 00011101 00000000 00000000 100 Loop tobeginning of control store

With regard to the present invention, it is apparent that there has beenprovided a Boolean processor. The architecture of the Boolean processoris optimized for monitoring and automation applications. The relativelysmall instruction set and design of the Boolean processor provide aninstruction savings of up to about 87.5% in relation to typicalmicroprocessor and microcontroller instruction sets. These instructionsavings and simple design provide the Boolean processor with high speed,in terms of instructions, as compared to other general-purposearchitectures performing similar functions. In addition to efficiency,the architecture of the Boolean processor is scalable. For example, ifthe Boolean processor is built with 32-bit addresses and 32-bit states,it can handle over about 4 billion (2³²) devices, each with over about 4billion possible states. The speed and scalability of the architectureof the Boolean processor make it a good candidate for large, criticalapplications, such as aeronautical and automotive monitoring, control,and automation applications.

As the number of sensors, or devices, increases, so does the amount ofwiring required for communications. Thus, serial communications may beused with the Boolean processor. Another advantage of the architectureof the Boolean processor is that it may be fitted with either a parallelor serial communications bus. A plurality of systems can also be used,each employing a Boolean processor designed to handle a large number ofsensors or devices specific to the given system. The individual systemscan communicate via another, smaller Boolean processor that is linked toeach of the systems as one of their devices. The smaller Booleanprocessor handles interactions among the systems. For example, considera braking system and a speedometer system in an automobile. The brakingsystem can be outfitted with numerous devices and sensors to control theapplication of the brakes, monitor temperature, and monitor pad wear, toname a few. Other systems in the car may only need to know whether ornot the brakes are being applied and whether or not there is a problemwith the entire braking system. The speedometer system can also beoutfitted with numerous devices and sensors for monitoring its ownhealth. Like the braking system, it only needs to communicate speed andgeneric warnings to the other systems in the car. Because each deviceonly needs to communicate two states, a smaller Boolean processor with asmaller bus that controls the interaction between these systems can beused, thereby saving wiring weight and confining complex communicationsinfrastructure to small areas of the vehicle.

Another potential use for the Boolean processor is as an interruptcontroller. A Boolean processor-based controller can enable amicroprocessor to be interrupted by an almost limitless number ofdevices. The Boolean processor acts as an “interrupt broker” for thedevices attached to it.

Although the Boolean processor of the present invention has beendescribed and illustrated with reference to preferred embodiments andexamples thereof, other embodiments and examples may be used and thefollowing claims are intended to cover all such equivalents.

1. A processing method, comprising: starting an operation related to aConjunctive Normal Form Boolean expression, wherein the Booleanexpression comprises a conjunct; evaluating the conjunct; andselectively short-circuiting a portion of the Boolean expression.
 2. Theprocessing method of claim 1, wherein the conjunct is a stand-alone termevaluated as an AND operation.
 3. The processing method of claim 1,wherein the conjunct comprises an OR clause.
 4. The processing method ofclaim 3, wherein each of a plurality of terms of the conjunct isevaluated as part of an OR operation.
 5. The processing method of claim4, further comprising setting the value of an OR-bit to ‘one’ if apredetermined term of the plurality of terms evaluates to true.
 6. Theprocessing method of claim 5, further comprising setting the value ofthe OR-bit to ‘zero’ if the predetermined term of the plurality of termsdoes not evaluate to true.
 7. The processing method of claim 6, furthercomprising, in a conjunct comprising an OR clause, OR'ing the result ofeach OR operation with the current value of an OR register.
 8. Theprocessing method of claim 7, further comprising, in the event that theOR register has a value of ‘one’ and an OR conjunct register is set to‘one’, evaluating the conjunct to true and short-circuiting to a nextconjunct.
 9. The processing method of claim 8, further comprisingjoining an AND operation and the next conjunct and rolling the value ofthe OR register up to the AND register by AND'ing the value of the ORregister with the value of the AND register.
 10. The processing methodof claim 9, further comprising, in the event that the OR-bit has a valueof ‘zero’ when the AND operation is processed, changing the AND-bit to avalue of ‘zero’.
 11. The processing method of claim 10, furthercomprising setting the final value of the Boolean expression to false,if the AND-bit has a value of ‘zero’, and short circuiting the remainderof the Boolean expression.
 12. A device polling unit for finding newdevices, assigning addresses to those devices, polling those devices fortheir current states, and updating a random-access memory with thosestates, the device polling unit comprising: a maximum device addresselectrically-erasable programmable read-only memory, wherein theelectrically-erasable programmable read-only memory is operable forstoring the highest address of all known devices on a system, whereinthe electrically-erasable programmable read-only memory comprises anincrement line that increments its value by one whenever it is assertedand a plurality of output lines that continuously output its value; ann-bit incrementing register, wherein the n-bit incrementing register isoperable for holding an n-bit number representing a current address of adevice being polled, wherein the n-bit incrementing register comprises areset line that sets the register to ‘zero’ whenever it is asserted, andwherein the n-bit incrementing register further comprises an incrementline and a plurality of output lines that continuously output its valueto an AND unit and a current address encoder; and wherein the devicepolling unit operates in a continuous loop after it is started.
 13. Thedevice polling unit of claim 12, wherein, if a new device is found and anew device found line is asserted, the device polling unit assigns asystem address to the new device via direct parallel communication orserially via a new address encoder.
 13. The device polling unit of claim12, wherein, if a new device is not found, the n-bit incrementingregister is incremented, the device polling unit polls the devicecorresponding to an address in the register, and the device polling unitcopies the device's current state into the random-access memory.
 14. Adevice interface unit for listening for new device seek, new address,state enable, and control line assertions and determining whether or notthere is work to do as a result of such assertions, the device interfaceunit comprising: a new device electrically-erasable programmableread-only memory, wherein the new device electrically-erasableprogrammable read-only memory comprises an n-bit store that is initiallyset to ‘one’, and wherein, when a new device seek line is asserted, then-bit store asserts a new device found line.
 15. The device interfaceunit of claim 14, further comprising an address decoder, wherein, if then-bit store is set, it allows an address passed on a new address line tobe placed in an n-bit address electrically-erasable programmableread-only memory and the n-bit store to be cleared.
 16. The deviceinterface unit of claim 15, further comprising a control word decoder,wherein the control word decoder is operable for reading serial bits offof a control line, and wherein, if an address matches the address in then-bit address electrically-erasable programmable read-only memory, aplurality of control bits output to a device controller to change itsstate.
 17. The device interface unit of claim 16, further comprising anaddress and state encoder, wherein the address and state encoder isoperable for reading bits in parallel that represent the address andstate of the device and serially outputs the bits to a receiver.